Jude Zhang

How to connect the APB bus to the generated verilog module？

3

hi, i want to use APB master to configure register. if i use ORDT to generate the register module, which processor interface do i should use? (Parallel processor interface, Leaf...

there is something error when openocd debug riscv multicore

7

Chip has 4 riscv cores, when openocd debug riscv multicore, riscv.cpu0 examine pass, but other cores encounter below errors: Error: 3406 6331102 riscv-013.c:1921 examine(): [riscv.cpu1] Debug Module did not become...

how to use debug tools during simulation stage？

5

Such as i want to use debug feature of risc-tests during Synopsys VCS or Cadence XRUN simulation?

hi，乔治，非常棒的工作，可是，你能有点耐心吗？继续进行下去。加油。

TriggerDmode case fail，when accessing 8-9 trigger

2

our riscv core vendor specify that tselect.index 0-7 can only be mcontrol, 8-9 can only be one of icount/ietrigger. TriggerDmode case trigger.S traverses the index from 0-9, and the type...