Jude Zhang

@sdnellen thanks, but why don't implement a apb bus or ahb bus register file? Copyright problem?

> Is there any example to demonstrate the usage of this script? Just clone this repo and submodule, then execute command in readme.

> Hi, I can't initialize the submodule for the Open_RegModel. Is the submodule still necessary? Sorry, Answering your question so late, the submodule is private before, i make submodule public...

> It's possible to do this, but I should warn you that these tests take a very long time to run in simulation. E.g. CheckMisa, which is one of the...

Hi， After a day of research I have found the problem, I modified my own target by referring to targets/SiFive/Freedom/U500Sim.py, but there is a problem in this script ``` def...

@timsifive As previous comment, i have run some testcase successfully. But i also found a little issue. If I set the jtag's clk to 200 MHZ, CheckMisa is wrong, if...

In addition to these cases, how long does each case run, I currently run to DebugFunctionCall, this case has been running for more than ten hours, I'm not sure if...

@en-sc Do you mean writing tdata1 with tdata1.type == 2 while tselect is 8 causes an illegal instruction exception on your HW? _Yes, it is._

Thanks for your help. I added 'debug_level 4' to the openocd config file. Is this the same as openocd -d3? Attatch is log file, search 'Error:' keyword. [20240326-150458-C920Sim-MulticoreRegTest.log](https://github.com/riscv-collab/riscv-openocd/files/14801685/20240326-150458-C920Sim-MulticoreRegTest.log)

@TommyMurphyTM1234 @en-sc Thanks. We are using a third party IP, AE suggested me to increase the tck between update_dr and idle, specifically to increase the number of tcks in the...