Jude Zhang

:snail:Yet Another Simulation Architecture

zhajio1988

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

zhajio1988

:ocean: Digital timing diagram rendering engine

zhajio1988

UVM resource from github, run simulation use YASAsim flow

zhajio1988

:candy:UVM candy lover testbench which uses YASA as simulation script

zhajio1988