Zihui Guo
Zihui Guo
**Describe the bug** When executing the **fmadd.d fa5, ft0, fa3, fa1, rtz i**nstruction in the XS, the resulting value in fa5 for a NaN outcome does not conform to the...
**Describe the bug** On the Kronos RISC-V processor, instructions that operate on non-existent Control Status Registers (CSRs) are executed successfully without raising an exception(as described in issue #9 ). This...
To fix #2012 The previous code would fail to exit normally under certain circumstances. For example, before exiting, `a0=0b01` (which becomes `0b10` after left shifting), so it is necessary to...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When performing floating-point division using the `fdiv.d` instruction in...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description In some rounding mode, precision errors occur when calculating...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description When executing the `fsqrt.d` instruction on a double-precision floating-point...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Description** I have encountered a bug where the NX...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description EDIT: The CVA6 can access an address beyond the...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Describe the bug:** In the CVA6 RISC-V core implementation,...
### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description **Describe the bug:** In the CVA6 architecture, executing an...