Zihui Guo

> Internally known issue as in https://github.com/OpenXiangShan/XiangShan-internal/issues/5 Hi @poemonsense, thank you for the response. I would like to confirm if this is indeed an issue with XiangShan, but I am...

> Hi! Nice catch @youzi27, despite apparently already known. Out of curiosity, how did you proceed for finding this issue? (Cascade maybe?) Thanks! Flavien Hi @flaviens ! It was through...

> Interesting. This is typically the kind of bugs that Cascade would find immediately. Did you have any difficulties with it? Excellent, but as far as I know, Cascade itself...

> It does :) . The only, small, effort that you would have to supply is to connect Cascade to it. More info in the bottom of the [Readme](https://github.com/comsec-group/cascade-artifacts). If...

The vulnerability of the rounding mode mentioned above also occurs in the `fdiv` instruction. **Example:** When executing the instruction `fdiv.d fs9, fs10, fa4` with the following register values: ``` fs10...

Hi @Nolan-Ashford . Thank you for your attention to this issue. However, in your response and the links you provided, I **did not** see any content related to the `DYN`...

Thank you for your attention to the issue. However, your response is inaccurate. Specifically: - Please read the issue I submitted carefully (see the NOTE section). This issue is **different...

Hi @riscv914, Thank you for your attention to this issue. Please use the pseudocode I provided to verify whether pre-clearing the `fflags` would affect the triggering of the NX bit....

Hi @JeanRochCoulon , If preserving the original information value is necessary, I believe it's also possible to `XOR a0` with another register to ensure that the value of `a0` is...

Hi @Moschn , Thank you for your prompt response. Spike throw a trap_load_access_fault exception. **Correction**: The above situation occurred in M mode(The CVA6 can access an insanely large address in...