[Bug report] Unexpected Behavior When Executing Instructions on Non-existent CSRs

[youzi27]

Describe the bug On the Kronos RISC-V processor, instructions that operate on non-existent Control Status Registers (CSRs) are executed successfully without raising an exception(as described in issue #9 ). This behavior is not only unexpected, as typically an illegal instruction exception would be anticipated, but it also has significant side effects. Notably, instructions intended to write 0x0 to the rd register, such as csrrsi, when executed with a non-existent CSR, result in a 0x0 being written to the rd register. This issue was observed with instructions like csrrsi a1, unknown_bb1, 0 #encoded as 0xbb1065f3, where unknown_bb1 represents an arbitrary, non-existent CSR.

Expected behavior: The expected behavior when executing an instruction that references a non-existent CSR is for the processor to raise an illegal instruction exception(as described in issue #9). Moreover, the value of the rd register within the CSR instruction should not be written as 0x0.

To Reproduce: An example is as follows:

1. Initialize a1 to any non-zero value,
2. Execute csrrsi a1, unknown_bb1, 0 (hardcoded as: 0xbb1065f3),
3. Observe that the value of a1 is written as 0x0.

Additional information This differs from issue #9 (where non-existent CSRs did not cause an illegal instruction exception) in a more crucial aspect: This differs from issue #9 (where non-existent CSRs did not trigger an illegal instruction exception) in a more severe manner: it alters the corresponding rd register when operating on non-existent CSRs.