Stephen Twigg

This is symptomatic of the more general issue that the design is not actually frozen when sent to the tester (after an emulator has been emitted). For example, trying to...

These seem functionally identical to a single entry queue where: For DCInput, flow is true, pipe is false For DCOutput, flow is false, pipe is true

I see the issue: the underlying desire is that the ready or valid ports be driven directly by a register. Although, this is still true in the single-entry queue case...

Does csr.io.rocc.resp.ready exist? If so, I think you should expect csr.io.rocc io.rocc to override the assignment. Would a dead code elimination pass help with resolving this class of issue?

Bundle.elements: LinkedHashMap[String, Data] is already available. So users already are free to write a function that connects two Bundles with different semantics (like the proposed filtering) than the current string...

As an addendum, ChiselMainTest does not have a run method (although it is still possible to test a Parameter-ized Module by using the alternative syntax).

Try removing the (7,0) from io.out and the origing io.out assignment. The signal is 8 bits wide so the (7,0) should be superfluous (although glitches in the internal implementation for...

I would go one step farther and say that you can only cross clock domains in Modules marked as permitting clock domain crossings. This saves us from having to special...

I suspect this is from: https://github.com/ucb-bar/chisel/blob/master/src/main/scala/Backend.scala#L140-144 Fixing this issue would require a rewrite of the naming logic to backtrack once a collision was found and assign the first user of...

Instantiating directioned nodes inside of a module but not in an I/O is dangerous. Try not defining those Bundles as I/Os (and then just using asInput and asOutput in your...