Stephen Twigg

Results 11 issues of Stephen Twigg

Currently, the only way to sanely inject a configuration object into a design is by appending --configInstance [string of config Instance class]. This is passable but the Class.forName(name) call is...

Feature Request

Any time you use scala extractor syntax (sometimes called doing an unapply), identifiers that start with an uppercase letter are assumed to be stable (already bound to a value) identifiers....

Documentation
Syntax

``` scala class Toy extends Module { val io = new Bundle { val in1 = UInt(width= 2).asInput val in2 = UInt(width=16).asInput val select = UInt(width= 2).asInput val out1 =...

Consider the following case: ``` scala class Toy extends Module { val io = new Bundle { val in = UInt(width=8).asInput val out = UInt(width=8).asOutput } val myDPT = Module(new...

``` scala UInt(1) // current syntax for constructing a UInt literal 1 // vs. UInt(width=1) // current syntax for constructing a wire of width 1 UInt(null, 1) // unadvised but...

Syntax

``` scala class Toy extends {val myEarlyReg = Reg(UInt())} with Module { val io = new Bundle { val in1 = UInt(width=2).asInput val out1 = UInt(width=32).asOutput } io.out2 := myEarlyReg...

A common issue with users is that Mem their designs are not being properly inferred to have the right ports. (For example, not merging related R and W ports into...

Feature Request

Previously, failure to specify the default for a wire (when using whens and similar) would give an error message indicate, at the very least, the name of the offending wire....

An arbiter has many producers trying to talk to a consumer. A work distributor has one (or more?) producers trying to talk to multiple consumers.

Feature Request

It seems somewhat weird to have two nearly identical ways of starting Chisel. Related to issue #309, it leads to divergent behaviors.

Feature Request