Stephen Twigg

What is the expected behavior? Also, so that we can reproduce the issue, what are the test inputs and expected outputs?

This is known and somewhat intentional. To improve readability, if a mux tree is used to feed a register, then the mux tree is replicated as if statements inside the...

In generally, allowing any Bool signal to be converted into a clock (that then ultimately drives registers) will likely end up (thoroughly) breaking the C++ backend and general combinational loop...

Do you have the same issue for non-debug compilations? Debug mode does increase the build complexity slightly (although usually moreso in compilation time, not required memory)

It is also tempting to deprecate ChiselMainTest; however, having the Tester in a separate parameter list invokes a nice Scala syntax trick where you don't have to specify the parameter...

It seems like this behavior was somewhat intentional: https://github.com/ucb-bar/chisel/commit/60c07086936fb7132d37c9e89b703566c87e3ffc intentionally turned off name disambiguation for modules with names explicitly set, apparently to address https://github.com/ucb-bar/chisel/issues/119 where blackboxes end up aggressively renamed....

A better approach for those desires again seems to hint at allowing you to override Bundle reflection to act in special cases. We already saw one case of this desire,...

Upon examination, I don't think this change will address scenarios from #392 (which I imagine is similar to Angie's issues?) due to https://github.com/shunshou/chisel/blob/master/src/main/scala/Vec.scala#L134 . Thus, you are likely to still...

The Chisel3 approach will (necessarily, due to FIRRTL incompatibility) removes the following way of updating registers: ``` scala val reg0 = Reg(init=UInt(0, width=4)) val wire1 = UInt(width=4) wire1 := UInt(0)...

This function handles all the edge cases properly I think https://github.com/sdtwigg/gama/blob/b268966af13312e7383e4821b6af4fc1a23fe5b4/chiselfrontend/src/main/scala/internal/BiConnect.scala#L39 None in the matching means an internal connectable node (like wire or reg), Some(Input/Output) is a port.