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                                            quanxianwang

[Intel-SIG] x86/CPU: support ClearWater Forrest(CWF) model and ISAs

Backporting two Clearwater Forrest commits to support new platform Clearwater Forrect(CWF) 090e3bec0176,x86/cpu: Add model number for Intel Clearwater Forest processor,2024-01-17 11:18:44,Tony Luck [[email protected]](mailto:[email protected]),v6.8-rc2 a0423af92cb3,x86: KVM: Advertise CPUIDs for new instructions...

[Intel-SIG] DMR new CPU model support

backporting two commits which is related with DMR CPU module support 70d1d98934e7,x86/cpu: Rename and move CPU model entry for Diamond Rapids,2025-09-17 11:22:11,Tony Luck [[email protected]](https://gitee.com/link?target=mailto%3Atony.luck%40intel.com),v6.18-rc1 d1fb034b75a8,x86/cpu: Add two Intel CPU model...

[Intel-SIG] new CPU topology series - 4/4: x86/apic: Rework APIC registration

dependency https://github.com/openvelinux/kernel/pull/102 https://github.com/openvelinux/kernel/pull/103 https://github.com/openvelinux/kernel/pull/104 CPU topology series: There are totally 5 series for this new cpu topology. 1st has been in 6.6, 2nd, 3rd, 4th, 5th series will be backported...

[Intel-SIG] new CPU topology series - 3/4: x86/topology: More cleanups and preparatory work

dependency https://github.com/openvelinux/kernel/pull/102 https://github.com/openvelinux/kernel/pull/103 CPU topology series: There are totally 5 series for this new cpu topology. 1st has been in 6.6, 2nd, 3rd, 4th, 5th series will be backported to...

[Intel-SIG] new CPU topology series - 2/4: x86/cpu: Rework the topology evaluation - part2

dependency https://github.com/openvelinux/kernel/pull/102 CPU topology series: There are totally 5 series for this new cpu topology. 1st has been in 6.6, 2nd, 3rd, 4th, 5th series will be backported to 6.6....

[Intel-SIG] new CPU topology series - 1/4: x86/cpu: Rework the topology evaluation - part1

CPU topology series: There are totally 5 series for this new cpu topology. 1st has been in 6.6, 2nd, 3rd, 4th, 5th series will be backported to 6.6. This PR...

[Intel-SIG] 5.15-ClearWater PMU support for core

this patch depends on PR#72 Intel-SIG: new Intel X86 CPU model definition support legacy enabling for PMU core part. 4a3fd13054a9,perf/x86/intel: Introduce pairs of PEBS static calls,2025-04-17 14:21:24,Dapeng Mi ,v6.16-rc1,v6.16-rc1 -...

[Intel-SIG] 5.15 - CWF PMU support for uncore and event

depends on PR#72 support Intel new platform Clearwater Forrest PMU for uncore and event 6d642735cdb6,perf/x86/intel/uncore: Support more units on Granite Rapids,2025-01-10 18:16:50,Kan Liang ,v6.14-rc1 3f710be02ea6,perf/x86/intel/uncore: Clean up func_id,2025-01-10 18:16:50,Kan Liang...

Intel-SIG: new Intel X86 CPU model definition

Note: this PR depends on #71, #72 is rebased on #71 for testing. These patches series are to backport new Intel CPU family model definition (IFM), only on common parts...

[Intel-SIG] Intel new platform ClearWater Forest support including CPU model/new ISAs and its dependency

Contents: 090e3bec0176,x86/cpu: Add model number for Intel Clearwater Forest processor,2024-01-17 11:18:44,Tony Luck ,v6.8-rc2 a0423af92cb3,x86: KVM: Advertise CPUIDs for new instructions in Clearwater Forest,2024-11-05 13:48:25,Tao Su ,v6.13-rc1 24d74b9f5f2a,KVM: x86: Advertise AVX-VNNI-INT8...