bytedance
[Intel-SIG] 5.15-ClearWater PMU support for core
this patch depends on PR#72 Intel-SIG: new Intel X86 CPU model definition
support legacy enabling for PMU core part.
4a3fd13054a9,perf/x86/intel: Introduce pairs of PEBS static calls,2025-04-17 14:21:24,Dapeng Mi [email protected],v6.16-rc1,v6.16-rc1 - added 25c623f41438,perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs,2025-04-17 14:21:24,Dapeng Mi [email protected],v6.16-rc1,v6.16-rc1 - added 48d66c89dce1,perf/x86/intel: Add PMU support for Clearwater Forest,2025-04-17 14:21:23,Dapeng Mi [email protected],v6.16-rc1,v6.16-rc1 149fd4712bcd,perf/x86/intel: Support Perfmon MSRs aliasing,2024-07-04 16:00:40,Kan Liang [email protected],v6.11-rc1 dce0c74d2d18,perf/x86/intel: Support PERFEVTSEL extension,2024-07-04 16:00:40,Kan Liang [email protected],v6.11-rc1 e8fb5d6e7658,perf/x86: Add config_mask to represent EVENTSEL bitmask,2024-07-04 16:00:39,Kan Liang [email protected],v6.11-rc1 608f6976c309,perf/x86/intel: Support new data source for Lunar Lake,2024-07-04 16:00:38,Kan Liang [email protected],v6.11-rc1,v6.11-rc1 090262439f66,perf/x86/intel: Rename model-specific pebs_latency_data functions,2024-07-04 16:00:38,Kan Liang [email protected],v6.11-rc1,v6.11-rc1 a932aa0e868f,perf/x86: Add Lunar Lake and Arrow Lake support,2024-07-04 16:00:37,Kan Liang [email protected],v6.11-rc1,v6.11-rc1 722e42e45c2f,perf/x86: Support counter mask,2024-07-04 16:00:36,Kan Liang [email protected],v6.11-rc1,v6.11-rc1 a23eb2fc1d81,perf/x86/intel: Support the PEBS event mask,2024-07-04 16:00:36,Kan Liang [email protected],v6.11-rc1,v6.11-rc1 950ecdc672ae,perf/x86/intel: Fix broken fixed event constraints extension,2023-09-12 08:22:24,Kan Liang [email protected],v6.7-rc1 - added 97588df87b56,perf/x86/intel: Add common intel_pmu_init_hybrid(),2023-08-29 20:59:23,Kan Liang [email protected],v6.7-rc1,v6.7-rc1 b0560bfd4b70,perf/x86/intel: Clean up the hybrid CPU type handling code,2023-08-29 20:59:23,Kan Liang [email protected],v6.7-rc1,v6.7-rc1 299a5fc8e783,perf/x86/intel: Apply the common initialization code for ADL,2023-08-29 20:59:23,Kan Liang [email protected],v6.7-rc1,v6.7-rc1 d87d221f854b,perf/x86/intel: Factor out the initialization code for ADL e-core,2023-08-29 20:59:22,Kan Liang [email protected],v6.7-rc1,v6.7-rc1 0ba0c03528e9,perf/x86/intel: Factor out the initialization code for SPR,2023-08-29 20:59:22,Kan Liang [email protected],v6.7-rc1,v6.7-rc1 d4b5694c75d4,perf/x86/intel: Use the common uarch name for the shared functions,2023-08-29 20:59:22,Kan Liang [email protected],v6.7-rc1,v6.7-rc1
PMU core test result: PASS
perf stat -a sleep 1
Performance counter stats for 'system wide':
145,420,198,486 cpu-clock # 144.133 CPUs utilized 604 context-switches # 4.153 /sec 145 cpu-migrations # 0.997 /sec 92 page-faults # 0.633 /sec 14,078,739 instructions # 0.30 insn per cycle 47,187,298 cycles # 0.000 GHz 2,809,817 branches # 19.322 K/sec 226,584 branch-misses # 8.06% of all branches
1.008929813 seconds time elapsed
[root@CS17CA101IS1502 ~]# perf record -e instructions -Iax,bx -b -c 100000 sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.034 MB perf.data (13 samples) ] [root@CS17CA101IS1502 ~]# perf record -e branches -Iax,bx -b -c 10000 sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.045 MB perf.data (29 samples) ]
