Philippe Sauter
Philippe Sauter
Verilator does not yet support all language constructs. This is particularly a problem for files in the 'simulation' target (not just in this repo but also in other repos like...
As it stands, the `cdc_2phase_clearable` module has a path going from the source clock domain into the destination clock domain directly, without a 2-flop synchronizer. The path in question is...
The [SRAM documentation](https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g2/libs.ref/sg13g2_sram/doc/RM_IHPSG13_1P_64x64_c2_bm_bist.txt#L96) for the `A_DLY` pin simply states: > Delay setting, adjustment of memory internal timings; recommended setting: Tie to 1 Its function does not seem to be further...
Work in progress. Adding a simple reference synthesis flow to Cheshire using yosys-slang. TODOs: - [ ] cva6_icache `error: cannot select range of 64 elements from 'logic[3:0]'` caused by a...
As far as I can see the only difference between `tc_sram_wrapper_cache_techno` and `tc_sram_wrapper` is that is adds `BYTE_ACCESS` which presumably communicates down if byte-enable is required. Otherwise it looks to...
fifo_v2 is deprecated and none of the special thresholding features unique to it are used here, so an update to fifo_v3 is trivial as it only removes the fifio_v2 from...