Philippe Sauter

I think there may have been a misunderstanding from what I said in another issue. SVase is intended as a standalone tool. It is fundamentally a SystemVerilog pre-elaborator built around...

Next week I am short on time as I will be at FSiC and then I om on vacation but I will try my best to compile them. We really...

I just had a look at `src/serial_deglitch.sv` and `src/mv_flilter.sv` both added in [this commit](https://github.com/pulp-platform/common_cells/commit/a954a44572723a90dc6a30860558a042c763099b). For `serial_deglitch` (as mentioned by others): - `q_o` has an incomplete assignment which means a latch...

Personally I am in favor of using the common cells assertions throughout the common cells themself. One thing we may want to keep is `COMMON_CELLS_ASSERTS_OFF` to turn off the asserts...

> I "could", but I'm not sure I see the point. Wireload models are so 1990. Nothing in the openroad/openlane flows use them (after placement steiner tree based parasitics are...

Its actually good to know that restructure is currently not supposed to be used, I was about to test if I can get some improvement out of it. At least...

This looks fine to me as the STA engine should properly time all paths anyway. We don't change or lose the described timing behavior so its also not an interface...

You should be able to use [yosys-slang](https://github.com/povik/yosys-slang) to read CVA6 into yosys, this should work without problem as it is one of the test cases used. As for synthesis flow,...

This already looks pretty good. Yosys-slang was able to parse and elaborate the entire tree otherwise it would have failed earlier. Giving the flist is the right thing to do...

@povik do you by chance see the problem from the error? It is coming from this function: https://github.com/openhwgroup/cva6/blob/master/core/include/aes_pkg.sv#L71