Fix non-synchronized path in cdc_2phase_clearable

[phsauter]

As it stands, the cdc_2phase_clearable module has a path going from the source clock domain into the destination clock domain directly, without a 2-flop synchronizer.
The path in question is in the reset/clear logic implemented in cdc_reset_ctrlr.
Specifically receiver_next_phase is clocked by the source domain (side A in cdc_reset_ctrlr) and then goes into the other side (side B) where it goes into i_state_transition_cdc_dst, a cdc_4phase_dst with the DECOUPLED parameter set to zero.
Setting this parameter to zero effectively bypasses the spill-register in there allowing the same asynchronous signal to leave and go into the destination clock domain, where it shows up as receiver_next_phase used to create the isolate and clear signals on the destination side.

I strongly doubt this is intended behavior and would like to fix this issue.

Further, this shows to me that especially the clock domain crossings need working testbenches that run in a CI to make sure they work as intended.
As part of this PR, I also started to fix the testbenches which in the case of cdc_2phase_clearable did not even test the module but presumably some old development version instead. This happened because the module is essentially copied in the testbench instead of actually testing the module itself.