Nils Wistoff

Hello, I also do not see anything preventing an FPGA implementation. The main effort would be setting up a system around Ara that instantiates the required Xilinx IPs, and getting...

Yes, that should be possible. However, AFAIK a single lane is approximately the size of Ariane. As a rule of thumb, we can fit two Arianes on the Genesys 2,...

I just realise that this solution might not be correct, as re-fetching from nonidempotent memory might be a violation. I guess a clean solution would be buffering the replayed instruction...

I encountered the issue when executing from Occamy's SRAM. I agree that in this specific case, we probably want to mark the SRAM as idempotent, but I think in general...

As far as I'm concerned yes, but the question is how to implement this correctly. As described above, the current implementation may deadlock (which this PR tries to fix). Also,...

@JeanRochCoulon that's up to you. From my point of view, this issue is still open as CVA6 may still dead-lock when executing from NI memory (which is currently permitted). But...

Hi, a few comments: 1. It looks like you are in kernel space when connecting gdb (i.e. Linux is booted). I understand that you would like to run a bare-metal...

I don't think so. AFAIK one can still configure a memory region as executable *and* non-idempotent, and the core might still dead-lock if one does so.

This seems to be a vopt bug in newer versions of questasim. They struggle with parametric data types, which are used in several of our IPs. I get the same...

Are the contents of `time` and `mtime` guaranteed to be equal then? Doesn't the spec allow for different implementations, e.g. by making `time` dependant on the system clock and driving...