pulp-platform
On the implementation of FPGA
Excuse me, do you have plans to release a fpga example project? This can actually run more programs better than simulation. cva 6 has related FPGA projects, but you seem to use many other peripheral ips.
I am currently trying to implement your design on FPGA. It is found that some functions, such as idx_width, under different Nrlane parameters, will not match the data bit width declared by you. For example, what you declare is a logic signal, but the idx_width may be limited by the bit width. Even if it is 1bit, the vivado software will report an error.I found some compilation parameters in your build folder, such as the compile.tcl , but I think these parameters seem incomplete.
Hello Fog-cake,
Thanks a lot for the inputs! We will have a deeper look at it. An FPGA project for Ara is planned, but not in the immediate future. Nevertheless, if you are interested, we would really appreciate your contribution and thoughts on this!
Hello, @mp-17 ,
Thank you for sharing such a great project!
Would you please let me know why don't you plan an FPGA-based Ara at the same time when starting the project? And what difficulties would be if we try to transplant the Ara on FPGA? I am strongly interested to implement the Ara design on FPGA.
Thanks in advance!!!
Hi @fantasysee,
Nothing prevents the implementation of Ara on an FPGA. It is just that the main developers of this project, both me and @mp-17, are working mainly on the ASIC implementation of this design. On Ara's side, we might use constructs that tools like Vivado do not understand, but I do not expect this to be too much of an issue. On CVA6's side, I believe they already provide an infrastructure to implement the design on an FPGA, which we might use to implement Ara.
I am adding my colleague @niwis to the conversation since he is the CVA6 and FPGA expert on the project. How hard do you think this would be?
Matheus
Hello,
I also do not see anything preventing an FPGA implementation. The main effort would be setting up a system around Ara that instantiates the required Xilinx IPs, and getting the constraints right. Also, the default FPGA for CVA6 (Kintex-7 on Genesys 2) is probably too small for Ariane+Ara.
Cheers, Nils
Thank you for your patient and warm reply, @suehtamacv and @niwis .
Best Regards, Chao
Hi, @niwis
Can I reduce the required FPGA resources by configuring parameters such as vlen? Thank you.
Yes, that should be possible. However, AFAIK a single lane is approximately the size of Ariane. As a rule of thumb, we can fit two Arianes on the Genesys 2, which would be equivalent to Ariane and a single-lane Ara. But there are larger FPGAs available
hello Which files is the top module if I want to implementation of Ara on an FPGA?
@Jett-tu You can follow up on this PR https://github.com/pulp-platform/ara/pull/146
