Nils Wistoff
Nils Wistoff
This bug was initially reported in #708. > Consider the following scenario while executing from nonidempotent memory: > > 1. A branch instruction is fetched => `speculative_d = 1'b1` >...
Prevent deadlock when replaying speculative instruction from nonidempotent memory region. Consider the following scenario while executing from nonidempotent memory: 1. A branch instruction is fetched => `speculative_d = 1'b1` 2....
Set Ariane's AXI data width to its data cache width (currently 512 bit) ## Changelog ### Changed - Update to CVA6 version with parametrised AXI data width - Separate AXI...
Flat ports are for instance required by the Vivado IP Integrator. Macro names are open for discussion :-) Based on https://github.com/pulp-platform/snitch/pull/91
The `modifiable` bit of `ax.cache` indicates whether an AXI transaction can be changed downstream (e.g. split, merged, etc.). This is needed by several AXI IPs. Based on https://github.com/pulp-platform/snitch/pull/96 and https://github.com/pulp-platform/snitch/pull/231.
Hi! When calling `SBI_SET_TIMER`, the passed argument is directly assigned to `mtimecmp`. Therefore, the argument is expected to be the absolute time the timer should trigger at. However, I cannot...
Using the latest version of riscv-gcc, the benchmarks compile incorrectly: `memset()` is compiled with a recursive call, just as described in https://github.com/riscv/riscv-gcc/issues/197. This leads to an infinite recursion and ultimately...
Add a module that converts wrapping bursts into up to two incremental bursts. The first incremental burst covers the region from the start address to the wrap boundary. The second...
There is a combinational path in `axi_to_mem` from `axi_req_i.b_ready` to `axi_resp_o.w_ready`. In particular, this is can be dangerous when connecting this module downstream of `axi_dw_downsize`, which has a comb path...
Add a verible CI job to lint the sources. ToDo: - [ ] Lint the sources to let this check pass.