glaserf

Results 7 comments of glaserf

Thanks for pointing this out. This is indeed an issue that we have seen in silicon. In the usual case where ``dmactive = 0``, all the registers are constantly written...

Regression results: ## CSRNG Simulation Results ### Sunday November 02 2025 20:38:25 UTC ### GitHub Revision: [`478cf94670`](https://github.com/lowrisc/opentitan/tree/478cf9467033c674e8f19da2887cbeeb969f3990) ### Branch: csrng_sfifo_removal ### [Testplan](https://opentitan.org/book/hw/ip/csrng/data/csrng_testplan.html) ### Simulator: XCELIUM ### Test Results | Stage...

Updated regression report: ## CSRNG Simulation Results ### Wednesday November 19 2025 18:51:19 UTC ### GitHub Revision: [`81bf64c98b`](https://github.com/lowrisc/opentitan/tree/81bf64c98bb9e964bf84a2d134da1d0788d4bd6a) ### Branch: csrng_sfifo_removal ### [Testplan](https://opentitan.org/book/hw/ip/csrng/data/csrng_testplan.html) ### Simulator: XCELIUM ### Test Results |...

> Looks like this only effects the latch implementation of the register file, which is why I think we didn't find it previously (as we simulate with the FF based...

Regression results: ## CSRNG Simulation Results ### Tuesday November 04 2025 09:55:03 UTC ### GitHub Revision: [`d16ce56753`](https://github.com/lowrisc/opentitan/tree/d16ce567539677e44a83ca5dda11e0dd90dbb9cc) ### Branch: csrng_sfifo_pr ### [Testplan](https://opentitan.org/book/hw/ip/csrng/data/csrng_testplan.html) ### Simulator: XCELIUM ### Test Results | Stage...

Is it really so hard to generate those file lists automatically (from verible itself)? Having to maintain them is something I'm not used to from other language servers (e.g., the...

Thank you so much. This keyboard is an absolute nightmare under Linux. The ctrl acting as brightnessdown is one of the most random things I ever came across. And the...