lowRISC
[csrng/rtl] Remove final three prim_fifo_sync from data path
Follow-up of https://github.com/lowRISC/opentitan/pull/28633 and https://github.com/lowRISC/opentitan/pull/28428, please see these PRs for details. This PR is the last part of this FIFO-removal series, removing three more FIFOs which together measure about 14kGE.
After this PR, there are in total three (was: 13) FIFOs remaining on the ctr_drbg data path. These cannot be removed due to the rather convoluted sharing of ctr_drbg_upd and the block_encrypt module. Removing any of the remaining FIFOs results in circular dependencies between these units. To get rid of these FIFOs, a general reorganization and simplification of the ctr_drbg data path is required, which will be another follow-up PR.
Please only review the last five commits. Commits before are part of https://github.com/lowRISC/opentitan/pull/28633.
Part of https://github.com/lowRISC/opentitan/issues/28153.
Regression results:
CSRNG Simulation Results
Sunday November 02 2025 20:38:25 UTC
GitHub Revision: 478cf94670
Branch: csrng_sfifo_removal
Testplan
Simulator: XCELIUM
Test Results
| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 7.000s | 26.546us | 50 | 50 | 100.00 % |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 2.000s | 93.435us | 5 | 5 | 100.00 % |
| V1 | csr_rw | csrng_csr_rw | 2.000s | 100.755us | 20 | 20 | 100.00 % |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 15.000s | 2.909ms | 5 | 5 | 100.00 % |
| V1 | csr_aliasing | csrng_csr_aliasing | 3.000s | 307.531us | 5 | 5 | 100.00 % |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 2.000s | 149.229us | 20 | 20 | 100.00 % |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 2.000s | 100.755us | 20 | 20 | 100.00 % |
| csrng_csr_aliasing | 3.000s | 307.531us | 5 | 5 | 100.00 % | ||
| V1 | TOTAL | 105 | 105 | 100.00 % | |||
| V2 | interrupts | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| V2 | alerts | csrng_alert | 26.000s | 4.494ms | 500 | 500 | 100.00 % |
| V2 | err | csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % |
| V2 | cmds | csrng_cmds | 6.567m | 66.227ms | 50 | 50 | 100.00 % |
| V2 | life cycle | csrng_cmds | 6.567m | 66.227ms | 50 | 50 | 100.00 % |
| V2 | stress_all | csrng_stress_all | 13.633m | 160.858ms | 46 | 50 | 92.00 % |
| V2 | intr_test | csrng_intr_test | 2.000s | 113.204us | 50 | 50 | 100.00 % |
| V2 | alert_test | csrng_alert_test | 9.000s | 55.724us | 50 | 50 | 100.00 % |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 5.000s | 670.667us | 20 | 20 | 100.00 % |
| V2 | tl_d_illegal_access | csrng_tl_errors | 5.000s | 670.667us | 20 | 20 | 100.00 % |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 2.000s | 93.435us | 5 | 5 | 100.00 % |
| csrng_csr_rw | 2.000s | 100.755us | 20 | 20 | 100.00 % | ||
| csrng_csr_aliasing | 3.000s | 307.531us | 5 | 5 | 100.00 % | ||
| csrng_same_csr_outstanding | 3.000s | 318.626us | 20 | 20 | 100.00 % | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 2.000s | 93.435us | 5 | 5 | 100.00 % |
| csrng_csr_rw | 2.000s | 100.755us | 20 | 20 | 100.00 % | ||
| csrng_csr_aliasing | 3.000s | 307.531us | 5 | 5 | 100.00 % | ||
| csrng_same_csr_outstanding | 3.000s | 318.626us | 20 | 20 | 100.00 % | ||
| V2 | TOTAL | 1436 | 1440 | 99.72 % | |||
| V2S | tl_intg_err | csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % |
| csrng_tl_intg_err | 16.000s | 1.443ms | 20 | 20 | 100.00 % | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 4.000s | 24.546us | 50 | 50 | 100.00 % |
| csrng_csr_rw | 2.000s | 100.755us | 20 | 20 | 100.00 % | ||
| V2S | sec_cm_config_mubi | csrng_alert | 26.000s | 4.494ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 13.633m | 160.858ms | 46 | 50 | 92.00 % |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_updrsp_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 26.000s | 4.494ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 13.633m | 160.858ms | 46 | 50 | 92.00 % |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 26.000s | 4.494ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 16.000s | 1.443ms | 20 | 20 | 100.00 % |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 2.000s | 253.298us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 9.000s | 1.730ms | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 71.456us | 500 | 500 | 100.00 % | ||
| V2S | TOTAL | 75 | 75 | 100.00 % | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 2.117m | 16.356ms | 10 | 10 | 100.00 % |
| V3 | TOTAL | 10 | 10 | 100.00 % | |||
| TOTAL | 1626 | 1630 | 99.75 % |
Coverage Results
Coverage Dashboard
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 97.64 % | 98.89 % | 97.31 % | 99.94 % | 96.83 % | 92.08 % | 100.00 % | 95.39 % | 89.84 % |
Failure Buckets
-
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReqhas 4 failures:- Test csrng_stress_all has 4 failures.
-
19.csrng_stress_all.73674456822232813723218088839237002501054921809006041481054885486479093715971
Line 177, in log /scratch/glaserf/opentitan/scratch/csrng_sfifo_removal/csrng-sim-xcelium/19.csrng_stress_all/latest/run.logUVM_ERROR @ 20675345664 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 20675345664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary --- -
20.csrng_stress_all.19712572081550793285328829292963901881167056310847698503663751519984229433200
Line 147, in log /scratch/glaserf/opentitan/scratch/csrng_sfifo_removal/csrng-sim-xcelium/20.csrng_stress_all/latest/run.logUVM_ERROR @ 12338085 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 12338085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary --- -
... and 2 more failures.
-
- Test csrng_stress_all has 4 failures.
INFO: [FlowCfg] [scratch_path]: [csrng] [/scratch/glaserf/opentitan/scratch/csrng_sfifo_removal/csrng-sim-xcelium] ERROR: [dvsim] Errors were encountered in this run.
[ legend ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]
00:00:10 [ build ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100%
00:19:11 [ run ]: [Q: 0, D: 0, P: 1626, F: 4, K: 0, T: 1630] 100%
00:19:17 [ cov_merge ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%
00:19:21 [ cov_report ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%
Updated regression report:
CSRNG Simulation Results
Wednesday November 19 2025 18:51:19 UTC
GitHub Revision: 81bf64c98b
Branch: csrng_sfifo_removal
Testplan
Simulator: XCELIUM
Test Results
| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 6.000s | 52.963us | 50 | 50 | 100.00 % |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 1.000s | 21.542us | 5 | 5 | 100.00 % |
| V1 | csr_rw | csrng_csr_rw | 2.000s | 132.623us | 20 | 20 | 100.00 % |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 5.000s | 415.080us | 5 | 5 | 100.00 % |
| V1 | csr_aliasing | csrng_csr_aliasing | 4.000s | 465.317us | 5 | 5 | 100.00 % |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 2.000s | 204.078us | 20 | 20 | 100.00 % |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 2.000s | 132.623us | 20 | 20 | 100.00 % |
| csrng_csr_aliasing | 4.000s | 465.317us | 5 | 5 | 100.00 % | ||
| V1 | TOTAL | 105 | 105 | 100.00 % | |||
| V2 | interrupts | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| V2 | alerts | csrng_alert | 32.000s | 6.551ms | 500 | 500 | 100.00 % |
| V2 | err | csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % |
| V2 | cmds | csrng_cmds | 3.667m | 48.086ms | 50 | 50 | 100.00 % |
| V2 | life cycle | csrng_cmds | 3.667m | 48.086ms | 50 | 50 | 100.00 % |
| V2 | stress_all | csrng_stress_all | 6.600m | 34.313ms | 50 | 50 | 100.00 % |
| V2 | intr_test | csrng_intr_test | 2.000s | 28.963us | 50 | 50 | 100.00 % |
| V2 | alert_test | csrng_alert_test | 6.000s | 26.447us | 50 | 50 | 100.00 % |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 4.000s | 623.248us | 20 | 20 | 100.00 % |
| V2 | tl_d_illegal_access | csrng_tl_errors | 4.000s | 623.248us | 20 | 20 | 100.00 % |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 1.000s | 21.542us | 5 | 5 | 100.00 % |
| csrng_csr_rw | 2.000s | 132.623us | 20 | 20 | 100.00 % | ||
| csrng_csr_aliasing | 4.000s | 465.317us | 5 | 5 | 100.00 % | ||
| csrng_same_csr_outstanding | 2.000s | 168.973us | 20 | 20 | 100.00 % | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 1.000s | 21.542us | 5 | 5 | 100.00 % |
| csrng_csr_rw | 2.000s | 132.623us | 20 | 20 | 100.00 % | ||
| csrng_csr_aliasing | 4.000s | 465.317us | 5 | 5 | 100.00 % | ||
| csrng_same_csr_outstanding | 2.000s | 168.973us | 20 | 20 | 100.00 % | ||
| V2 | TOTAL | 1440 | 1440 | 100.00 % | |||
| V2S | tl_intg_err | csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % |
| csrng_tl_intg_err | 12.000s | 1.531ms | 20 | 20 | 100.00 % | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 6.000s | 14.062us | 50 | 50 | 100.00 % |
| csrng_csr_rw | 2.000s | 132.623us | 20 | 20 | 100.00 % | ||
| V2S | sec_cm_config_mubi | csrng_alert | 32.000s | 6.551ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 6.600m | 34.313ms | 50 | 50 | 100.00 % |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_updrsp_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 32.000s | 6.551ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 6.600m | 34.313ms | 50 | 50 | 100.00 % |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 32.000s | 6.551ms | 500 | 500 | 100.00 % |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 12.000s | 1.531ms | 20 | 20 | 100.00 % |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| csrng_sec_cm | 6.000s | 73.860us | 5 | 5 | 100.00 % | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 8.000s | 346.985us | 200 | 200 | 100.00 % |
| csrng_err | 6.000s | 21.420us | 500 | 500 | 100.00 % | ||
| V2S | TOTAL | 75 | 75 | 100.00 % | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.717m | 11.332ms | 10 | 10 | 100.00 % |
| V3 | TOTAL | 10 | 10 | 100.00 % | |||
| TOTAL | 1630 | 1630 | 100.00 % |
Coverage Results
Coverage Dashboard
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 97.64 % | 98.87 % | 97.25 % | 99.91 % | 96.83 % | 92.08 % | 100.00 % | 95.40 % | 90.11 % |
INFO: [FlowCfg] [scratch_path]: [csrng] [/scratch/glaserf/opentitan/scratch/csrng_sfifo_removal/csrng-sim-xcelium]
[ legend ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]
00:00:54 [ build ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100%
00:13:56 [ run ]: [Q: 0, D: 0, P: 1630, F: 0, K: 0, T: 1630] 100%
00:14:26 [ cov_merge ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%
00:14:30 [ cov_report ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%
CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_top.sv
This PR is part of a bigger restructuring effort for CSRNG previously discussed in different WG meetings. The coverage and test pass rates remain at very high rates. This is fine.
CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_top.sv
This PR is part of a bigger restructuring effort for CSRNG previously discussed in different WG meetings. The coverage and test pass rates remain at very high rates. This is fine.
