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[csrng/rtl] Remove three prim_fifo_sync from the data path

Open glaserf opened this issue 3 months ago • 1 comments

Follow-up of https://github.com/lowRISC/opentitan/pull/28428; removes three more FIFOs which together measure about 13kGE. Apart from everything mentioned in https://github.com/lowRISC/opentitan/pull/28428, removal of the affected FIFOs required the following changes:

  • Rework the state db cycle-alternating "arbitration". As there never is a need where both the ctr_drbg_cmd and _gen units want to write to the state db at the same time, the actual arbitration logic can be kept very simple.
  • Introduce a small FSM to ctr_drbg_cmd that handles the bifurcation of the data stream and waits on commands that require the ctr_drbg_upd unit for both it and the cmd_rsp channel being ready before signaling the cmd_req as ready.

Part of https://github.com/lowRISC/opentitan/issues/28153.

glaserf avatar Nov 02 '25 15:11 glaserf

Regression results:

CSRNG Simulation Results

Tuesday November 04 2025 09:55:03 UTC

GitHub Revision: d16ce56753

Branch: csrng_sfifo_pr

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 9.000s 246.853us 50 50 100.00 %
V1 csr_hw_reset csrng_csr_hw_reset 2.000s 233.282us 5 5 100.00 %
V1 csr_rw csrng_csr_rw 1.000s 13.902us 20 20 100.00 %
V1 csr_bit_bash csrng_csr_bit_bash 11.000s 1.385ms 5 5 100.00 %
V1 csr_aliasing csrng_csr_aliasing 3.000s 273.440us 5 5 100.00 %
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 2.000s 294.328us 20 20 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 1.000s 13.902us 20 20 100.00 %
csrng_csr_aliasing 3.000s 273.440us 5 5 100.00 %
V1 TOTAL 105 105 100.00 %
V2 interrupts csrng_intr 10.000s 313.847us 200 200 100.00 %
V2 alerts csrng_alert 18.000s 2.210ms 500 500 100.00 %
V2 err csrng_err 8.000s 24.949us 500 500 100.00 %
V2 cmds csrng_cmds 3.167m 37.836ms 50 50 100.00 %
V2 life cycle csrng_cmds 3.167m 37.836ms 50 50 100.00 %
V2 stress_all csrng_stress_all 8.217m 84.965ms 49 50 98.00 %
V2 intr_test csrng_intr_test 1.000s 14.493us 50 50 100.00 %
V2 alert_test csrng_alert_test 8.000s 15.735us 50 50 100.00 %
V2 tl_d_oob_addr_access csrng_tl_errors 4.000s 175.366us 20 20 100.00 %
V2 tl_d_illegal_access csrng_tl_errors 4.000s 175.366us 20 20 100.00 %
V2 tl_d_outstanding_access csrng_csr_hw_reset 2.000s 233.282us 5 5 100.00 %
csrng_csr_rw 1.000s 13.902us 20 20 100.00 %
csrng_csr_aliasing 3.000s 273.440us 5 5 100.00 %
csrng_same_csr_outstanding 2.000s 104.462us 20 20 100.00 %
V2 tl_d_partial_access csrng_csr_hw_reset 2.000s 233.282us 5 5 100.00 %
csrng_csr_rw 1.000s 13.902us 20 20 100.00 %
csrng_csr_aliasing 3.000s 273.440us 5 5 100.00 %
csrng_same_csr_outstanding 2.000s 104.462us 20 20 100.00 %
V2 TOTAL 1439 1440 99.93 %
V2S tl_intg_err csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
csrng_tl_intg_err 5.000s 815.392us 20 20 100.00 %
V2S sec_cm_config_regwen csrng_regwen 8.000s 60.852us 50 50 100.00 %
csrng_csr_rw 1.000s 13.902us 20 20 100.00 %
V2S sec_cm_config_mubi csrng_alert 18.000s 2.210ms 500 500 100.00 %
V2S sec_cm_intersig_mubi csrng_stress_all 8.217m 84.965ms 49 50 98.00 %
V2S sec_cm_main_sm_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_updrsp_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_update_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_outblk_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_ctrl_mubi csrng_alert 18.000s 2.210ms 500 500 100.00 %
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
V2S sec_cm_constants_lc_gated csrng_stress_all 8.217m 84.965ms 49 50 98.00 %
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 18.000s 2.210ms 500 500 100.00 %
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 5.000s 815.392us 20 20 100.00 %
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
csrng_sec_cm 9.000s 179.763us 5 5 100.00 %
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 10.000s 313.847us 200 200 100.00 %
csrng_err 8.000s 24.949us 500 500 100.00 %
V2S TOTAL 75 75 100.00 %
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 2.583m 12.978ms 10 10 100.00 %
V3 TOTAL 10 10 100.00 %
TOTAL 1629 1630 99.94 %

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.59 % 98.76 % 96.96 % 99.85 % 96.77 % 92.08 % 100.00 % 95.53 % 90.12 %

Failure Buckets

  • UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
    • Test csrng_stress_all has 1 failures.

      • 42.csrng_stress_all.7201815913989753525406440744181533782652175777971277456600672816489512363970
        Line 146, in log /scratch/glaserf/opentitan/scratch/csrng_sfifo_pr/csrng-sim-xcelium/42.csrng_stress_all/latest/run.log

          UVM_ERROR @ 5722333422 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5722333422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

INFO: [FlowCfg] [scratch_path]: [csrng] [/scratch/glaserf/opentitan/scratch/csrng_sfifo_pr/csrng-sim-xcelium] ERROR: [dvsim] Errors were encountered in this run.

          [   legend    ]: [Q: queued, D: dispatched, P: passed, F: failed, K: killed, T: total]                                                                                                                                                             
00:01:04  [    build    ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100%                                                                                                                                                                                         
00:17:11  [     run     ]: [Q: 0, D: 0, P: 1629, F: 1, K: 0, T: 1630] 100%                                                                                                                                                                                   
00:17:41  [  cov_merge  ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%                                                                                                                                                                                         
00:17:45  [ cov_report  ]: [Q: 0, D: 0, P: 1, F: 0, K: 0, T: 1] 100%

glaserf avatar Nov 02 '25 15:11 glaserf

CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_main_sm.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_top.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_state_db.sv

This PR modifies the RTL of CSRNG to remove more area and simplify the design. The changes are part of a bigger restructuring effort which has been discussed in multiple WG meetings. The pass rate and coverage remain above the V2(S) thresholds. This is fine.

vogelpi avatar Nov 05 '25 20:11 vogelpi

+1 fr DV changes.

phani-lowrisc avatar Nov 07 '25 11:11 phani-lowrisc

CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_main_sm.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_pkg.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_reg_top.sv CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_state_db.sv

This PR modifies the RTL of CSRNG to remove more area and simplify the design. The changes are part of a bigger restructuring effort which has been discussed in multiple WG meetings. The pass rate and coverage remain above the V2(S) thresholds. This is fine.

andreaskurth avatar Nov 10 '25 18:11 andreaskurth