Brian Sune

> Hi all, > > I would like to ask if any people encounter the soft-UART only work after boot / program the FPGA and stop working after plug and...

Hi all, First i would like to appreciate the great work from "David Williams". Second with ZYNQ 7010 i have no issue no the RTL implementation and testing loop-back. So...

I have also tested with Spartan 7. No problem found with hot plug reset as well. 

First OMG those data are amazing! Great~ Meantime I am on the same page of "They are not meant to compete with hardened CPUs." However, idea is that if there...

Hello, Success! Network also working and apt is working as well. ` RISC-V 64, Boot ROM V3.4 OpenSBI v1.0 ____ _____ ____ _____ / __ \ / ____| _ \_...

@dontfollowmeimcrazy i do have the same situation with your posted code. If learning rate is set to 1e-2 the loss drop logically, while after 1 epoch the loss saturate and...

Able to digitize between ~0 to ~3.3V is a tricky description. Which what I experience is a digitized offset range from 1xxx to 64xxx. Of cause meaning 0 to 3.3V....

In my quick testing now I've determined when you change the OVERSAMPLE_RATE and CIC_STAGES you should accordingly change the ADC_BITLEN parameter to match. The output is always going to be...

 So from simulation it shows a sine wave with offset range. However, idle in simulation is not the case. What I am really can't figure out is that can...

Dave, my default setup is using oversample = 256 otherwise 2 stage CIC cannot form a 16bit resolution as your code clearly suggested. So Dave, are you really achieving 14bit...