Brian Sune
Brian Sune
Hi all, I would like to ask if any people encounter the soft-UART only work after boot / program the FPGA and stop working after plug and un-plug the USB...
Hello, First really appreciate the magnificent RISC-V project.  I had successfully run debian on the single RISC-V big core on Artix 7 but I am facing some concern here....
@Zhouaojun Would you mind refresh the INQ caffemodel library, which some files seems missing. Thanks
Updated the RTL generate errors (labeling is missing at generate for loops)
Hi, After reviewing a bit the HW schematic, there are couple of questions come to my mind. 1) NFC usually only require bandwidth of 14kHz so if we filter and...
I had tested with 16 bit 2+8 setting of 2 stage CIC and 8 oversample under 6.25M. Any detail formula of the RC selection and the low and high side...
The rtl8822bs ap is also broken. And there is crash log behind the dmesg ``` [ 1662.131006] ------------[ cut here ]------------ [ 1662.131023] Have pending ack frames! [ 1662.131095] WARNING:...