antmarzam

- SPI host agent now waits a couple of extra clock_cycles when the read_pipeline delay is enabled. - The read_pipeline feature has been added and enabled (randomly) to the cmd_info...

### Description The spi-host TB doesn't currently do error_status.accessinval verification. This issue is meant to track ACCESSINVAL stimulus needed, checking and coverage.

[spi_host] ACCESSINVAL error set, tl-ul bus error not signalled.

1

### Description When writing to the TX FIFO only 1/2/4 bytes masks are allowed, any other combination means the write will be discarded but no error is signalled back at...

[dv, spi_host] Re-implementing command.CSAAT <-> CSB check

3

Plus a bit of cleanup for unused variables and a warning from a VSEQ

[spi_host, dv] data stable SVA check fix

3

Previous SVA check had a race condition. The change simplifies the whole check and has been regressed against VCS and Xcelium

[dv, rom_ctrl] inject u_checker_fsm.u_compare.start_i error when not …

2

Before injecting errors in `start_checker_q` ensure there's not an ongoing ping. This is done first by checking the VIF hasn't already detected a ping, and then waiting for the ping...

Extern tasks added to alert agent

2

Making tasks/functions/constraints `extern` for `alert_esc_agent`