[spi_host] ACCESSINVAL error set, tl-ul bus error not signalled.

[antmarzam]

Description

When writing to the TX FIFO only 1/2/4 bytes masks are allowed, any other combination means the write will be discarded but no error is signalled back at the TL-UL interface. The valid strobes are defined here

You can see an example below, where the mask is 0x7, which causes an ACCESSINVAL error, but the TL-UL bus doesn't raise the d_error signal:

Is this the intended behaviour?

cc: @a-will / @vogelpi / @andreaskurth / @hcallahan-lowrisc

[andreaskurth]

Thanks for reporting this, @antmarzam. As the invalid write gets signaled to SW through ERROR_STATUS.ACCESSINVAL, I think we don't urgently need to also signal an error through d_error. We might want to add the latter in the future, though, so I'm assigning this to Backlog and Future Release.