Albert Magyar

Eager use of FIRRTL 1.4+ dedup can cause issues with bridge connectivity annotations

2

So far, there has been a sequence of three successive workaround/fixes that have gradually moved closer to ideal FIRRTL dedup performance. 1. Turn off dedup entirely with a global `firrtl.transforms.NoCircuitDedupAnnotation`...

Currently, models (or target design memories) that use true dual-port memories cannot efficiently map to BRAMs due to mismatches in FIRRTL Verilog generation and BRAM behavior. The "FPGA backend" introduced...

Connect source to sink in RationalCrossingFull

4

**Type of change**: bug report **Impact**: no API changes **Development Phase**: implementation I don't think the full "crossing in its own module" was being used.

Added support for successive <> operations overriding each other.

2

I implemented and tested out both varieties of overriding bulk connects, letting `:=` override `` and letting `` override ``, and I think a good case can be made for...

A while ago, I added a check that elaborates the declared fields of a class and examines whether methods share names with fields to determine whether they are `val` accessors...

This depends on ucb-bar/chisel3#436 to change `IrrevocableIO` to a subtype of `DecoupledIO` and to make `EnqIO` (for the output of `Queue`) return an `IrrevocableIO`.

Replace CHIRRTL with new behavioral memory statements

1

**Type of change:** bug fix / improvement **API impact:** API addition **Backend code-generation impact:** Fixes open issues with CHIRRTL memories and associated enables This subsumes #1210 List of issues with...

Should MacroCompiler emit FIRRTL in addition to Verilog

1

The FIRRTL output got dropped in #80 Please comment here if you would like it back.