Albert Magyar

I bumped this, as it's still relevant. In light of what we've seen so far with recent subtle Verilog-emission bugs, it would be good to add a couple tests and/or...

One thing to point out is that this does have an API impact, since people would have to change code that extends `MultiTargetAnnotation`. That should be fine for 1.3 (master),...

> @albert-magyar wouldn't it infer the type parameter to be `Target`? Unfortunately, it won't generally infer the type parameter for the trait, since Scala only has local type inference. Not...

I'll preface this by saying that I don't think this is a showstopper by any means, but more of a heads-up about the potential holes in the type safety of...

`SingleTargetAnnotation` has a [specific check for illegal renames](https://github.com/freechipsproject/firrtl/blob/35febeaf80998a1f9449dda2cc869550753f4f5a/src/main/scala/firrtl/annotations/Annotation.scala#L65). It's generally pretty ugly, but the TLDR is that it does a duplicate call with the actual returned target inside `update` to...

Moving declarations or definitions might fix compile-time errors, but the Chisel C++ simulation model depends on the ability to provide a linearization of the update graph for one clock cycle...

Can you provide example code? I tried reproducing it, but got something like `instance_0` in my output.

In Chisel 2, you can set the name (as emitted by a backed) of any wire to be whatever you like by invoking setName(name: String).

If it's that simple that's a really embarrassing bug in ISE.

And HDL developers will already have lots of experience with `use strict; use warnings` :)