Himal Subedi

>>Through the Lsu2Plugin, its has 2 pipeline, one for load/store execute, one for store writeback The Load and store buffer is connected to the CPU through the Load and Store...

Hi Charles, could you please help me to figure out ? Thank you

Hi, I did in this way. this way of implementation of **dirty evict** gives me 22 times more counting than **write back counter** My way is following ``` add(l2c.events.evict.clean, 0xF28)...

>> Can you show me the code were evict.dirty is defined ? i defined as below: val acquire = new Area{ // NEWLY ADDED val hit, miss = False //...

How can we remodify our **dirty evict** so it can measure L2 writeback to the main memory

Thank you. nice idea Can you please advise the appropriate way how to incorporate the core number that initiated the downstream request so that we can later use it for...

as givenCpuThrottle comes from cache miss counter or from a memory-mapped counter ``` scope.add(l2.cache.logic.cache.events.acquire.miss.pull() || l2.cache.logic.cache.events.getPut.miss.pull(), 0xF30)``` How can I throttle specific core based on per Miss counter, which is...

Previously i did so I incremented the counter by +1 as long as there is cache miss in **every cycle**. i used later that **counter** to create some algorithm for...

Thank you so much. Will it be possible to merge to the main branch of git because when I compile i just **copied the necessary updated part of code** and...

thank you can you please tell me how you compile (all steps please) the files which are in different git branch ? How is it possible to see in gtkwaves...