Himal Subedi

Thank you so much :) i am curious how can i get **play.elf** file when i run compile myself

**sbt "runMain naxriscv.Gen64" && make -C src/test/cpp/naxriscv compile** can we do it by staying main branch in NaxRiscv and in dev branch in spainalHDL ?

ok i stay in **throttle_l2** in Main hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_throttle_branch/NaxRiscv$ git branch -a main * throttle_l2 remotes/origin/HEAD -> origin/main remotes/origin/asic remotes/origin/cleaning remotes/origin/coherency remotes/origin/dev remotes/origin/fast-reschedule remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready remotes/origin/fpu remotes/origin/jtag remotes/origin/lsu2 remotes/origin/lsu_peripheral_store_cmd_ahead remotes/origin/main remotes/origin/reuse_licenses remotes/origin/riscv-debug...

I get some errors by *git checkout throttle_l2* ``` hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_2_throttle_branch/NaxRiscv$ git branch -a * main remotes/origin/HEAD -> origin/main remotes/origin/asic remotes/origin/cleaning remotes/origin/coherency remotes/origin/dev remotes/origin/fast-reschedule remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready remotes/origin/fpu remotes/origin/jtag remotes/origin/lsu2 remotes/origin/lsu_peripheral_store_cmd_ahead remotes/origin/main remotes/origin/reuse_licenses...

Thank you so much 🙏 🙏 How to use **play.elf** where we can find files to load in GTK waves ? & which file is it (e.g. VCD) ? seems...

still i face errors ``` [info] [Warning] toplevel/toplevel_naxes_1_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into Verilog [info] [Warning] 1695 signals were pruned. You can call printPruned on the...

mine is **Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad** kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/simWorkspace/SocDemo$ verilator --version Verilator 4.038 2020-07-11 rev v4.036-114-g0cd4a57ad

i updated it and later i get another problem now i have **Verilator 4.216 2021-12-05 rev v4.216** ``` [info] [Progress] Simulation workspace in /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/NaxRiscv_4_throttle_branch/NaxRiscv/./simWorkspace/SocDemo [info] [Progress] Verilator compilation started [info]...

I did so **sbt:NaxRiscv> runMain naxriscv.platform.tilelinkdemo.SocSim --load-elf play.elf --trace --nax-count 2 --no-rvls** did i did correctly ? ``` [info] [Warning] toplevel/toplevel_naxes_0_thread_core_DataCachePlugin_mem_toTilelink_coherent_onC_rspFifo/logic_ram : Mem[16*42 bits].readAsync can only be write first into...

Thank you so much :) I did new git clone of whole project recursively run litex of Nax core with L2 core ``` python3 -m litex_boards.targets.digilent_arty --variant a7-100 --cpu-type naxriscv...