Himal Subedi
Himal Subedi
I dont know where the issue is either with litex or with Nax core ( with L2 cache). ``` python3 -m litex_boards.targets.digilent_arty --variant a7-100 --cpu-type naxriscv --xlen 64 --cpu-count 1...
Still didnot solve my problem i get following errors while compiling in litex with ``` python3 -m litex_boards.targets.digilent_arty --variant a7-100 --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 4096 --update-repo no...
full output of console is here ``` hsubedi@kronos:~/instruction_test_bed/litex/fpga_nax_3$ python3 -m litex_boards.targets.digilent_arty --variant a7-100 --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 4096 --update-repo no --build Namespace(toolchain='vivado', build=True, load=False, log_filename=None, log_level='info', flash=False,...
> And you did update litex ? Also, did you deleted the litex's naxriscv python data generated verilog ? yes
>Should be socClk. >In NaxSoc.scala, do you have "val socClk = in Bool()" ? yes now it is working fine in Litex but there is some probelem in standalone NAX...
full error is here ``` di@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull$ git clone --recursive https://github.com/SpinalHDL/NaxRiscv.git Cloning into 'NaxRiscv'... remote: Enumerating objects: 10689, done. remote: Counting objects: 100% (1634/1634), done. remote: Compressing objects: 100% (753/753), done....
If we want to do it in FPGA ( litex), Does **the PLIC / CLINT / Scope memory mapping limit** matter **without rearranging it's internal memory mapping**?
>>doesn't occur in a single point I guess we might need to write different if else statement ``` add((masterHit && l2c.events.acquire.miss).setCompositeName(l2c.events.acquire.miss, s"nax_$i"), i * 0x80 + 0x40) ``` I wonder...
>>Why not, to make some space, could be more, could be less Is it for the L2 cache? As L2 is an inclusive cache, which has a copy of L1...
Thank you, Do we also need to care of the inclusive part of the L2 cache to estimate the refill and writeback of L1 cache within `if (withL2) {}` block?...