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                                            Jett-tu

On the implementation of FPGA

hello Which files is the top module if I want to implementation of Ara on an FPGA?

您好：我把memory_0_axi4总线和一个带AXI4总线的RAM连接在一起。把peripheral_0_axi4总线通过Vivado的axi_interconnect连接到一个SD和uart16550上面。SD卡存放运行的指令。 dma_0_axi4的总线没有做处理。 input io_clock, 接30M的时钟信号。 input io_reset, 接复位信号，高复位 input [4:0] io_sram_config, 接5‘h0 input io_osc_clock, 接1’h0 output [13:0] io_pll_output, 默认 input [149:0] io_extIntrs, 将uart16550的中断信号接到这里 input io_systemjtag_jtag_TCK, input io_systemjtag_jtag_TMS, input...

Question concerning AXI bus

不好意思，不太明白您的意思，这个随机初始化具体加在哪里？是加在XSTop.v这个文件，用define来进行定义。还是在运行make verilog命令带上这些define？ [TRANSLATION]Sorry, I don't quite understand what you mean. Where is this random initialization specifically added? It is added to the file XSTop.v and defined using define. Or...

Question concerning AXI bus

是的，我借助VCS和Vivado来进行仿真测试。根据您这边的建议，我将define加在XSTop.v文件中的module XSTop的前面。但是从总线上观测，两条总线上都不存在读/写的行为。 [TRANSLATION]Yes, I used VCS and Vivado for simulation testing. According to your suggestion, I added define before module XSTop in the xstop.v file. However, as observed...

Question concerning AXI bus

我的设想是这样的，两组总线都接到带AXI4的接口的RAM上面，我在testbench给出时钟和复位信号。这样是否可以观测到总线的读写行为？另外，您们指令是放在哪里的？是通过那条总线去读取第一条指令的？ [TRANSLATION]My vision is that both buses are connected to RAM with an AXI4 interface, and I give clock and reset signals in testbench. Is it possible to...

Question concerning AXI bus

是Peripheral还是memory这条总线进行读操作？ [TRANSLATION]Is the Peripheral or memory bus used for read operations?

Question concerning AXI bus

在模块中去追这个peripheral_0_araddr[30:0]这个信号初始是由那个模块的赋值的。感觉有点绕。能否指出其初始值是在那个模块？当然我也可以把我的顶层和仿真顶层发给您，看是否哪里激励给的不正确。麻烦了！ [TRANSLATION]In the module to trace this peripheral_0_araddr[30:0] this signal was originally assigned by that module. It feels a little messy. Can you tell us which module the...

Question concerning AXI bus

我发现在香山很多模块中用到以下代码。 `ifdef RANDOMIZE_MEM_INIT integer initvar; initial begin #`RANDOMIZE_DELAY begin end for (initvar = 0; initvar < 64; initvar = initvar+1) ram[initvar] = {128 {$random}}; reg_RW0_addr = {1 {$random}}; end `endif...

Question concerning AXI bus

您好，请问三条总线的地址空间划分是怎么划分的。当前我只知道外设总线的起始地址是31‘h1000_0000,那么它的终止地址是到哪里，另外，memory总线和DMA的总线的地址是如何划分的。 [TRANSLATION]Hello, may I ask how to divide the address space of the three buses? At the moment, I only know that the start address of the peripheral...

Question concerning AXI bus

如果我挂一个DDR3的控制器，用于控制外围的DDR3颗粒，应该和DMA的总线连在一起。而不是和memory的总线连在一起？可以这么理解？那memory总线是访问什么外设的？ [TRANSLATION]If I attach a DDR3 controller, which controls the peripheral DDR3 particles, it should be connected to the DMA bus. Instead of connecting to the memory bus? Can...