Florian Zaruba

Failure to detect cache coherency violation.

2

Location: cva6/src/cache_subsystem (https://github.com/openhwgroup/cva6/tree/master/src/cache_subsystem). Details: According to the RISC-V specification, when the instruction memory is modified, the software should handle the cache coherency using FENCE.I instruction. If the input program modifies...

Divider Rounding Issues

2

> There is still work to do on sub-normalised divides but this is repeatable and unrelated. For example 2.350988561514729E-38 / 2 => 0. (it should give 1.175494350822288E-38, a subnormal value)...

Consolidate SV32 and SV39 MMUs

1

Right now the files are mostly copies of each other but the differences are not small enough so that we can use SV parameters to capture them so we would...

*Issue #, if available:* The logs can be sensitive (i.e., by running proprietary software) and it should be possible to hide them. *Description of changes:* This change introduces an additional...

Manually transferring this issue from here: https://github.com/openhwgroup/cva6/issues/577#issue-782170535 When I am trying to synthesize the design, It gives me an error in this function; `any_enabled_multi` in `fpnew_opgroup_block.sv` `Error: ../cva6/src/fpu/src/fpnew_opgroup_block.sv:81: Constant value...

This makes it impossible to instantiate a 32-bit address and 64-bit data module.

CI/CD Bring-up

12

Install continuous delivery of FPGA bitstreams for: - Genesys 2 - Nexys A7 I've already set-up the required FPGA container. The remaining challenges are: - [ ] Make sure PULPissimo...

Remove `xilinx_interleaved_ram` and `xilinx_private_ram`

1

Block RAMs can be inferred using either the correct coding style or Xilinx Parameterized Macros (XPM) such as used in the `tc_sram`s.

Re-think FPGA specific modules

1

Currently the FPGA and ASIC specific modules are `ifdefed` and scattered throughout the code. I would propose two fixes to that: - SRAMs are wrapped in technology unspecific ways. During...

Remove global header files from IPs

1

Searching all IP repositories for `pulp_soc_defines.sv` (`rg -w pulp_soc_defines -g '!core-v-mcu/*'`) leads to: ``` cluster_interconnect/rtl/peripheral_interco/AddressDecoder_PE_Req.sv 46:`include "pulp_soc_defines.sv" ``` IPs should be stand-alone and should not depend on includes. Let's refactor...