Florian Zaruba
Florian Zaruba
Thinking about it a bit more (and dumping it here), we probably want to limit some paths through the crossbar and to make it a bit simpler. For example a...
Thanks for putting this together. This looks very, very promising. There is currently only one thing which came to my mind: Regarding the interface wrapper for multiple slave or master...
I don't have any objections to the hardware architecture. I'd probably designed it very similarly. The stream-based description approach makes the RTL very, very readable. Nice work.
@DaveMcEwan Indeed I agree after looking into the Language Manual. Interesting, that most of the tools have no problem with the `;` though. p. 781 also gives an example: ```verilog...
I think a configuration struct makes the most sense. As far as I know that is being supported in every tool.
Unfortunately, I am still skeptical about the solution here. The debug module should, ideally, support all variations of `XLEN` and `BusWidth`. It is unclear to me what happens in your...
From an RTL perspective I'd say we need to prioritize: ``` IMPLICIT 220 PINMISSING 149 MULTIDRIVEN 3 ``` which, unfortunately, make up quite some amount of pins... Before we start...
It actually got worse. The waiver file has been compromised during merging outdated branches. I think we are back at square one with this.
For sure legacy. Never heard of it.
In fusesoc we would already have a solution for this, it supports generate targets and it generates the files into a build dir which is unique for the given target,...