yushi96

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unsupport concat type when parse dataflow.

你好，请问你也使用pyverilog编译AES设计了吗？我想编译AES，并获得其dataflow，结果跑了好久都没出结果。但我跑uart的时候，很快。请问你知道为什么吗？

unsupport concat type when parse dataflow.

那你最后跑出来了嘛？我现在需要提取verilog设计中的数据流，我自己写不来编译器，只能找轮子，他这个感觉还可以哦发自我的华为手机-------- 原始邮件 --------主题：Re: [PyHDI/Pyverilog] unsupport concat type when parse dataflow. (#36)发件人：hunterzju 收件人：PyHDI/Pyverilog 抄送：yushi96 ,Comment 你好，请问你也使用pyverilog编译AES设计了吗？我想编译AES，并获得其dataflow，结果跑了好久都没出结果。但我跑uart的时候，很快。请问你知道为什么吗？ 可能是有解析过程有环，导致无限循环了，貌似pyverilog对有环的情况处理不太好，可以top命令看一下是不是进程一直在吃内存。 —You are receiving this because you commented.Reply to this email directly, view it on...

unsupport concat type when parse dataflow.

Sorry

Slow dataflow analysis

hi，i use dataflow analysis analyze AES design, it had spent one day.now, it still running. i want to know why?

Slow dataflow analysis

Thanks for your reply . so, if I have enough time and LINUX platform has enough memory, no matter how large design always can analyze? such as : c8051

Slow dataflow analysis

I want to extract dataflow from the verilog design (uart,AES,c8051). But I can't write the verilog compiler front end. so , I read your paper and find pyverilog. about my...