yportne13

allow blackbox io read from verilog

4

use macro to read a verilog code and can directly use those signals in scala, helpful for import a verilog blackbox. a demo is provided: `PlayParser.scala`

Some little change on inout signal

6

1. remove `{` `}` 2. add size `[1:0]` 3. align brackets 4. add comment `//~` 5. remove `analog_wrap` 1.10.1: ```verilog MyBlack b ( .io_ttttttttttttttttttttttttt (b_io_ttttttttttttttttttttttttt[1:0]), //o .io_x ({analog_wrap_0}) ); assign...

create more analog signal than need

10

```scala class InOut extends Component { val b = new MyBlack val a = new MyBlack val c = new MyBlack val ret = Analog(Bits(2 bit)) b.io.x := ret c.io.x...

Bug: in ps_or_hierarchical_net_identifier, hierarchical_net_identifier will never use

1

at https://github.com/dalance/sv-parser/blob/v0.13.1/sv-parser-parser/src/general/identifiers.rs#L502 line 502 should move down to line 505 for example, when parse `interface_a.sig_b`, `interface_a` is a net_identifier so `ps_or_hierarchical_net_identifier_package_scope` parse success. but it should be a hierarchical_identifier

Add doc about SVIF (system verilog interface)

2

for this pr: https://github.com/SpinalHDL/SpinalHDL/pull/1364

set rst name for default clock domain by ClockDomainConfig

3

I have to name rst signal to `rst_n` instead of `resetn`

# Context, Motivation & Description # Impact on code generation # Checklist - [ ] Unit tests were added - [ ] API changes are or will be documented: -...