yportne13

> > Hi ^^ > > a few questions : > > * Does it handle Verilog parameters ? > * Would it be possible to generate a string of...

you can find it by searching onioncc/iSmartDNN

可以魔改 codeshell 的 vscode 插件 ^_^ 我试过用 llama.cpp 的 server 起一个 mistral-7b 搭配 codeshell vscode 插件，只需要修改插件内置的 prompt 改成 mistral 的格式就能正常使用了 ^_^

`assign` an analog signal might lead to the insertion of digital buffers in some eda tools. To avoid generating such code, two modifications [phase.scala#389](https://github.com/SpinalHDL/SpinalHDL/pull/1319/files#diff-0ae53b8431a1d28d269ed1e47ce1e97ad2bddcb8ccbcb3eb656fe5474d2e5bddL389) and [phase.scala#419](https://github.com/SpinalHDL/SpinalHDL/pull/1319/files#diff-0ae53b8431a1d28d269ed1e47ce1e97ad2bddcb8ccbcb3eb656fe5474d2e5bddL419) were made but it...

maybe something like this? ```scala val count = filtred.count(e => e.isInOut && e.component == c) val countA = filtred.count(e => e.isAnalog && e.component == c) count match { case 0...

change e.isInOut to e.isAnalog will leads to **MULTIPLE INOUT** bug ignore this, on official 1.8.2 version, i found another bug: ```scala class InOut extends Component { val io = new...

i don't know, maybe the second case is also no possible to write in verilog, but if so, maybe spinal should raise error instead of generate this strange code? for...

when you write such a code in verilog: ```verilog //rtl.v assign analog_a = analog_b ; ``` it is possible to get something looks like this after synthesis: ```verilog //netlist.v (DC/RC_SYNC)...

> Have you seen SpinalHDL emiting such broken verilog ? yes, look at the beginning of this issue, this case generate such a line > ```verilog > assign ret[1 :...

why not convert to BigInt? ```scala def stringToBigInt(x: String): BigInt = { x.getBytes() .map(x => BigInt(x)) //.reverse .reduce(_ * 256 + _) } ```