viktorinox

Are the verilog config are supported ?

4

I'm trying to use configs for some test bench: > config tb_cfg; > // Define top > design tb_lib.tb; > /* rules begin */ > default liblist lib1 lib2; >...

regression works when running sequentially but fails when using multiple threads

19

I'm using Vunit with verilog/systemverilog and xcelium I have a strange issue. When in my setup I use multiple thread with the option: python run.py --num-threads 5 Some tests are...

Recompile RTL with GUI open

3

I've been facing the following issue and I don't know if there is a limitation or there is another way to do it. First I'm launching a test interactively with...

Verilog Vunit does not fail when there is an error

7

The first issue I encounter is because of line 138 of file vunit_pkg.sv, when I launch a test it doesn't end. I had to replace the $stop by $finish (Running...

The following syntax doesn't compile in Pyverilog assign (weak1,weak0) vreg1p65= 1'b1;