Hideto Ueno

[ExportVerilog] Enable new emission mode by default

2

This PR switches ExportVerilog emission mode to new simplified version by default. `useOldEmissionMode` flag is added to use the old emission mode. If there is no problem for a few...

[FIRRTL/IMCP] Suboptimal results with invalid states

4

```mlir firrtl.circuit "Example" { firrtl.module private @Test(in %in1: !firrtl.uint, in %in2: !firrtl.uint, in %clock: !firrtl.clock, out %out: !firrtl.uint) { %r = firrtl.reg %clock : !firrtl.uint %0 = firrtl.or %in1, %r...

`circt-opt -export-verilog` crashes with this IR (https://godbolt.org/z/1qxzPva35) since seq.compreg is expected to be lowered before ExportVerilog (`circt-opt -lower-seq-to-sv -export-verilog` compiles https://godbolt.org/z/7666xaz7v). However it would be nice to emit good error...

```scala circuit Foo: module Foo: input in1: UInt[2] input in2: UInt[2] input cond: UInt output o: UInt[2] when cond: o

[FIRRTL] Use EnumAttr for `sym_visibility` of `InnerSymPropertiesAttr`

2

Currently `sym_visibility` uses `StringAttr` as a container but `sym_visibility` is either `public` or `private`. Therefore, it would be cleaner to use enum attr to represent visibility. https://github.com/llvm/circt/blob/04797976d2ccdb6e3d1f8ecdc9dee60cc3d5a8c5/include/circt/Dialect/FIRRTL/FIRRTLAttributes.td#L203-L208

[SV] Generic SVAttributes

8

Currently SVAttributes are intentionally limited to sv.reg, sv.wire(https://github.com/llvm/circt/commit/761b6107e78f8ef89576754731ff5367a1b9060f) and sv.assign(https://github.com/llvm/circt/commit/3a13fbf0530d66fc1048a7b5ec901725e951241d), e.g: ```mlir %bar = sv.reg svattrs [#sv.attribute] sv.assign %bar, 0 svattrs [#sv.attribute] ==> (* foo *) wire bar; (* baz...

[ExportVerilog] Initial statement needs begin/end for single declaration

1

Input: ```mlir hw.module private @Foo() -> (){ sv.initial { %param_x = sv.localparam : i42 { value = 11: i42 } } } ``` `$ circt-opt -export-verilog` produces: ```verilog module Foo();...

[PrepareForEmission] Temporaries are not spilled in a procedural region

2

The following IR is derived from a test case of https://github.com/llvm/circt/pull/3116 which workarounded verilator hangs. ```mlir hw.module @Verilator3405() -> () { %state = sv.reg : !hw.inout sv.initial { %state_read =...

[FIRRTL] Unused 0-bit firrtl.invalidvalue remains after LowerToHW

3

Input: ```mlir firrtl.circuit "Foo" { firrtl.module @Foo() { %invalid_ui0 = firrtl.invalidvalue : !firrtl.uint } } ``` Output of `circt-opt -lower-firrtl-to-hw` contains `firrtl.invalidvalue` for some reason. ``` hw.module @Foo() { %invalid_ui0...

[ExportVerilog] Weird wire/assign statement indent

1

I haven't reduced yet but I have often seen indent around wire/assign broken. For example, in `DivSqrtRecF64_mulAddZ31` module in [FPU.fir](https://github.com/circt/perf/blob/trunk/regress/FPU.fir) compiled with `firtool -drop-names`, there is code like this: ```verilog...