Hideto Ueno

> Or a lowering option for LowerToHW that would skip these attributes entirely. Yeah, I think it makes sense to create an option to attach pragmas if there is actual...

Thank you for working on 0bit support! I agree with Mike about the concern and I'm wondering we can handle 0bit width in the very late pipeline such as PrepareForExpression/ExportVerilog....

Thanks! I'll take a look at the details later but there are several counterexamples right now that need to be fixed: ```mlir hw.module @Concat(%arg0: i0, %clk: i1) -> (out: i1)...

I'm in flavor of making these pragmas optional (ref:https://github.com/llvm/circt/issues/3828). But if we made the pragmas optional for HWMemSimImpl, we should align LowerToHW too.

> There should be module control and perhaps instance control. Hmm, interesting. I think currently we don't have a good mechanism to control this from Chisel/FIRRTL (except for annotations). Is...

> Can we get this in using the same global control as the other MUX pragmas. That will allow groups to generate the RTL both ways to compare and contrast...

Added a flag `-strip-mux-pragmas` to control mux pragmas of LowerToHW and HWMemsimImpl

> Looks good. Can I grep for 'builder.createhw::ArrayGetOp(array, index);' to identify other potential annotation locations? Yes I think it makes sense to grep `AraryGetOp`. As far as I see, LowerToHW...

Thanks! The change makes sense to me! One issue we have is that the current result of memory.fir is like this: ```verilog always @(posedge clock) begin memory

I'm not sure making `preserve_type` attribute into ODS defined one is a good idea since that attribute is used by only LowerTypes :thinking: