Tiago Gomes

Running multiple threads with Questa fails

26

I have an issue when running multiple threads using the Questa simulator and the flag `-p`. I created a minimal example to reproduce the issue. The testbench implements a single...

I was very surprised to find an assertion in a VUnit component that has no message. See line [uart_slave.vhd#L63](https://github.com/VUnit/vunit/blob/8fcbf595c09d7b46b224fb9140843ade70953f35/vunit/vhdl/verification_components/src/uart_slave.vhd#LL63C7-L63C14) and line [uart_slave.vhd#L71](https://github.com/VUnit/vunit/blob/8fcbf595c09d7b46b224fb9140843ade70953f35/vunit/vhdl/verification_components/src/uart_slave.vhd#LL71C7-L71C14). When no message is specified in an `assert`...

Fix warning "(vcom-1246) Range 1 to 0 is null" for Modelsim/Questa.

5

This is a minor fix to avoid unnecessary warnings with Questa and Modelsim.

The Avalon stream slave component does not support non-blocking 'pop_avalon_stream()' while the AXI stream slave component does by using 'pop_axi_stream()' together with 'await_pop_axi_stream_reply()'. This updates the Avalon stream slave with...

Speed-up compilation of Vivado libraries

2

I use the following command to compile the Vivado libraries: `$(GHDL_PATH)/lib/ghdl/vendors/compile-xilinx-vivado.sh --unisim --vhdl2008 --source $(VIVADO_PATH)/data/vhdl/src --output $(VENDOR_LIB_RELDIR)/$(SIMULATOR_NAME)` When using the debug flag `-d`, I noticed that GHDL compiles each component...