Feature Request: Improve VHDL UART Slave verification component

[tasgomes]

I was very surprised to find an assertion in a VUnit component that has no message.

See line uart_slave.vhd#L63 and line uart_slave.vhd#L71.

When no message is specified in an assert statement then a generic message is printed:

# ** Error: Assertion violation.

As noticeable, the testbench will just stop due to an error and it is completely impossible to track down where and which entity generated this error. After losing a good amount of time, I realized the error was coming from the UART Slave VC.

Also, because this VC supports no loggers/checkers, then when multiple UART slave VCs are used, it is also impossible to verify from the error message which specific UART slave triggered the error.

This really a bad practice and should be fixed. My recommendation would be to replace the assert statements by the VUnit Checker API (using meaningful error description messages) and to add support to logger/checkers so that multiple UART slaves can easily be identifiable on the console log.