sylefeb
Due to the way Verilog inputs/outputs are written by Silice, and limitations of the import, Silice cannot directly re-import the modules it exports.
A versioning approach needs to be defined: - tags on `master` branch on new versions (when merging from `wip`), where the tag is an actual version string (good practices?) -...
Following discussion in #219 there is a cleaner way to write the compilation scripts (calls to gcc, the `compile_c.sh` bash scripts in project files). Scripts could use an update overall.
Trackers defined in pipeline stages are not properly tagging trickling variable usage. The trickling vios used in the tracker are not seen as used and end up being optimized out....
There are several limitations when binding to outputs: - ~~Partial bindings (with bit/part select) is unsupported, an error is correctly reported~~ a first prototype is in draft, requires testing and...
Extra pins would be tagged onto the input/output. This would give extra flexibility when a specific feature is not exposed in the framework, or when the pins are used in...
Allow at least 'access' (table, io, etc.) for inputs.
In practice, it is quite typical to write a design with a single, infinite while loop, most often in an autorun algorithm. The synthesized Verilog in that situation is too...
Sometimes one may want to pass additional options to yosys or nextpnr (or the toolchain in general). These options can be changed in the board.json, but it could be good...