Shinya T-Y comments

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                                            Shinya T-Y

SV parse error

SytemVerilog support is under development on feature_systemverilog branch. Stay tuned!

ast.IntConst creates collisions on dicts

Thanks for the nice suggestion. Could you show us what kind of adverse effects are occurred by the current implementation? Furthermore, I wonder just adding "lineno" is sufficient.

Enhancement: Support for SystemVeirlog

Unfortunately, I don't have any plan to extend the language feature of Pyverilog. Pyverilog uses Icarus Verilog as a preprocessor. If we don't develop preprocessor by ourselves, Pyverilog overcome the...

Suggestion for clock and reset recognition

Thank you for a good suggestion. As you said, the current isReset and isClock are defined just by using a simple rules of signal names, and it is possible to...

Suggestion for clock and reset recognition

Thank you for a nice idea. I think it can be implemented within a small effort. After that, let's replace the current name-based implementation with it.

Suggestion for clock and reset recognition

I'm sorry for the delay. Actually I did not understand the behavior of the updated version of bind_visitor._createAlwaysinfo(). I think choice 3 is the best currently.

Added end_lineno to indicate the last line number in always, module, …

Thanks! Let me review the code.

Better Documentation/Tutorials

> HTML docs hosted somewhere I should prepare such documents ...

unsupport concat type when parse dataflow.

Hi, could you use English, please?

Slow dataflow analysis

I think it's because the current dataflow analyzer does not use memorization.