Enhancement: Support for SystemVeirlog

[amal-khailtash]

Is there a plan to support SystemVerilog 2012?

[shtaxxx]

Unfortunately, I don't have any plan to extend the language feature of Pyverilog.

Pyverilog uses Icarus Verilog as a preprocessor. If we don't develop preprocessor by ourselves, Pyverilog overcome the language feature of Icarus Verilog.

I don't know how many features of SystemVerilog Icarus Verilog supports. Do you have any easy pointers for implementing SystemVerilof features with Icarus Verilog?

Thanks

[fukatani]

One method is convert systemverilog to verilog before preprocessing.↓ http://electronics.stackexchange.com/questions/78834/systemverilog-to-verilog-translation

But part of systemverilog feature are challenging (interface, enum, struct, union). Personally, my group don't use interface, enum, struct and union. I use only always_comb, always_ff and logic. So I appreciate if Pyverilog support them ( or I will implement. ).

[amal-khailtash]

As for preprocessor, you can use https://github.com/wsong83/vpreproc that is a standalone port of Wilson Snyder's Verilog-Perl preprocessor. That could be translated to PLY because it is lex/yacc based already.

I can help with the SystemVerilog grammar. I have worked on PLY version, but it needs some more work.