qgzln
qgzln
> Try to use: conda activate base & python3 You need to specific your python executable. TerosHDL runs: conda activate base & python3 --version El lun., 29 nov. 2021 7:06,...
> Could you check if you have the same problem in the beta version? > > https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/V0.0.5 I have the same problem in the beta version
> Could you explain the problem in more detail? when i use generate template to generate some template such as cocotb testbench etc,the template is on clipboard， so i want...
> > > Could you check if you have the same problem in the beta version? > > > https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/V0.0.5 > > > > > > I have the same...
> > > Could you check if you have the same problem in the beta version? > > > https://github.com/TerosTechnology/vscode-terosHDL/releases/tag/V0.0.5 > > > > > > I have the same...
> Yes, it does. There is a large number of user in Windows 10. > > Most of the problems are with environment configuration or collisions with other vscode extensions...
> In the next release we will support it. But only for VHDL. El vie., 23 abr. 2021 3:49, qgzln ***@***.***> escribió: > […](#) > I find that the plug...
Thank you for your reply.It is my fault.I didn't make it clear, I mean there is no case in the generated Verilog statement, I usually use the case when writing...
只有opencl的代码对吧，只能运行在intel的FPGA上？
请问有没有硬件部分较为详细的设计文档，我想根据OPENCL代码来用chisel或Verilog来进行RTL级的实现