msaideroglu
msaideroglu
Hi. I'm trying to do PnR of an OpenFPGA. My technology node is 250nm. So DFF chain based architectures cost a huge area because of DFF's. To be able to...
When I try to running full_testbench task with a SOFA architecture file, and choose layout size as 2x2, I am getting this type of error on openfpgashell.log: `Error 1: bb_cost_check:...
I was working on a Uart benchmark in **k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm** arch. When I compare Vivado synthesis results with Yosys synthesis, I'm seeing important difference in terms of LUT numbers used. The...
I um running **/openfpga_flow/tasks/fpga_verilog/bram/dpram1k** task. It successfully completes as displayed in shell. However preconfigured testbench can not display true results. All Ram input and outputs are displaying 1'bx as well...
I'm running a basic and2 benchmark with basic full_testbench task on K4N4 and K4_frac_N4 architectures that OpenFPGA repo includes. However I'm seeing different routing results when I check VPR visualizations....
I cloned clear fpga caravel repo and trying to reproduce outputs myself. The repo url is: [https://github.com/efabless/clear](url) There is an interactive.tcl script in /openlane/fpga_core design. How can I run this...
There is an interactive.tcl script that includes interactive flow commands. How to use it to harden fpga_core. Also there is a synt_top.tcl written in config.tcl that is missing. @mkkassem @Manarabdelaty
I want to compile the model with a 32 bit Single Precision FP GPU. How should I deactivate double precision? I could'nt find that config param in src/opencl.c or src/opencl.h.