msaideroglu

Results 9 comments of msaideroglu

Some questions about Memory Bank Protocol

Thanks a lot for your detailed explanations.

CCFF Design in 2019 FPL Paper

Hi @egiacomin. Could you give me the details about the design above?

Preconfigured testbench not working but full_testbench does

Hi @tangxifan. I am facing the same issue described above. I um running **/openfpga_flow/tasks/fpga_verilog/bram/dpram1k** task. It successfully completes as displayed in shell. However preconfigured testbench can not display true results....

Benchmarking a FIFO circuit

Hi @tangxifan. I'm facing same issue. How should I change Yosys script?

Full testbench is working but preconfigured testbench and behavioral benchmark are giving 1'bX

Hi @tangxifan. I added that initial state in **_OpenFPGA/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v_** . However the result was same as before.

32 bit Single Precision FP

Hi Piotr. Thank you for your return. I want to compile and run your Darknet model in Vortex GPGPU Design. It is an open-source RISC-V based GPGPU Design from Georgia...

32 bit Single Precision FP

Hi Piotr. In ARM mode enabled, it doesnt give any other serious error except some solvable warnings. However the performance is terrible in comparison with CLBLAS. So, I need to...

32 bit Single Precision FP

I found the source of error. My OpenCL implements **barrier(CLK_LOCAL_MEM_FENCE)** but not **mem_fence(CLK_LOCAL_MEM_FENCE)**. mem_fence(CLK_LOCAL_MEM_FENCE) gives **Cannot find symbol _Z13_cl_mem_fencej in kernel library**. The error is coming from mem_fence(CLK_LOCAL_MEM_FENCE) in CLBLAS...

32 bit Single Precision FP

Thanks. I've already found out sth. about it.