Moritz Imfeld

Results 13 issues of Moritz Imfeld

Hi @michael-platzer ## Issue Narrowing instructions, namely `vnsrl.(wv|wx|wi)`, `vnsra.(wv|wx|wi)` and `vnclip(u).(wv|wx|wi)`, are never popped from the instruction queue in the `vproc_core` module. This will eventually cause the queue to run...

Hi @michael-platzer A vector widening multiply accumulate instruction does a `SEW` * `SEW` multiplication and adds the product to a 2*`SEW` value. The result will have a width of 2*`SEW`....

Hi @michael-platzer, ## Issue Sometimes the multiply unit does not output the correct result. I think the issue does not lie in the multiplier itself but in the control logic....

Hi @michael-platzer, ## Issue Vicuna does not check source register validity before accepting instructions. This will lead to wrong results (or memory access to wrong addresses). ## How to reproduce...

Hi @michael-platzer I remember that you told me at one point that the masking for some instructions does not work. Nevertheless I open this issue to create an overview of...

Hi @michael-platzer, ## Issue For `LMUL=1/2` or `LMUL=1/4` the result is not calculated correctly. For the `vslidedown.vi v8, v1, 7` instruction (`SEW=8`, `LMUL=1/4`, `VL=8`) the UVM environment throws the following...

Hi @michael-platzer ## Issue Comparison instructions should write the result of each comparison into the corresponding mask element of the result register. Vicuna does this, but it also updates the...

Hi @michael-platzer, ## Issue I think there is a problem with the computation of the averaging subtract (`vasub(u).(vv|vx)`) instructions. For example, when executing the instruction `vasub.vv v22, v14, v9` with...

Hi @michael-platzer When executing the vzext.vf2 instruction on Vicuna the UVM environment issues the following warning (and error): # UVM_WARNING uvm/src/env/cvxif_scoreboard.svh(207) @ 2430: uvm_test_top.env.scoreboard [CVXIF_SCOREBOARD] Instr "vzext.vf2 v4, v0 e16,...

bug

Hi @michael-platzer, when using the `VPORT_POLICY=many` policy, the Makefile can generate configurations where the maximum `PIPE_W` is equal to `VREG_W`. When one `PIPE_W` is equal to `VREG_W` then the `MAX_OP_W`...

bug