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Update on regression results on 03/18/2024: 
I undated the issue to state it only applies to rstmgr, not clk or pwrmgr.
In rstmgr_reset_vseq we apply random resets, which include hard (aon) and regular resets, so this issue can be declared complete.
Regarding difs, we had to develop templated difs for otp_ctrl. I have also seen is asked what are the specific points of customization for some top-specific IPs. This is handled...
Changing the milestone past M4.
As @cindychip pointed out, the CIP infra resets every CSR, but in some blocks not all CSRs get the same reset. Unfortunately this is done in the dv_base_scoreboard's reset, so...
More details: both *info_ctrl CSRs have an index field, reset by POR, and an enable bit, cleared on any hardware reset. So their reset behavior is even more nuanced. There...
An update: there is a number of rstmgr CSRs that are reset only by POR, including alert and cpu_info_ctrl. It turns out all fields in these CSR are reset by...
These duplicate license headers don't get generated by the ipgen flow, so they will be gone once #8440 is complete. As it stands the ones in rstmgr are already gone.
The initialization happens via flash_crl_mp_info_page_cfg from the given page_cfg. The caller passes mp_info_pages[bank][info_type][$] (last dim is the per info type number of pages). Pages in question are mp_info[any][0][0..3] should have...