lsteveol

changes for output assigns

2

This is a *hopeful* solution to https://github.com/SpinalHDL/SpinalHDL/issues/251 that I raised. ComponentEmitterVerilog.scala ----------------------------- - Added a check where if an output of a subcomponent was connect to an output of the...

Remove assigns for direct connections to output

6

I wondering if something like this can be adjusted. Similar to https://github.com/SpinalHDL/SpinalHDL/issues/132. If I have a Bundle that I use up a hierarchy, outputs seem to get reassigned. Here is...

Custom ChipTop/DigitalTop and Configs

6

I have been trying to figure out a clean-ish way to support different `ChipTop/DigitalTop` instances and `Config`s based on certain use cases. For example I have added some custom AXI/TL...

**Type of issue**: bug report ( ?) (probably incompetency :)) **Impact**: API modification | unknown **Development Phase**: request | proposal **Other information** **If the current behavior is a bug, please...

CentOS Binaries for releases

5

In some of the latest releases I've noticed macos/ubuntu precompiled binaries (which thank you!). Is it possible to add in Centos7 to this list?

[FIRTOOL] -verilog flag should not include firrtl_black_box_resource_files.f

2

As discussed in https://github.com/llvm/circt/issues/2254 , `firtool -verilog` will append the contents of the `firrtl_black_box_resource_files.f` file into the output verilog file. This results in non-compliant verilog. Since these BlackBox modules are...