lsteveol
lsteveol
Interesting, I tried that release a few weeks back and was getting a GLIB error, now I don't see that. I do have the following ``` firtool: error while loading...
I'm on CentOS 7 (from 2019) currently. If it was easy to add to the release flow, I'd love it but don't want to sound too pushy. But I do...
Constructing the clock tree in that manner will usually avoid the delta cycle issue in digital simulation as well. I have been working on a DSL that sits on top...
Did this feature ever make it into Chisel3.x or FIRRTL? I've done some searching and I haven't been able to pinpoint a solution.
Thanks! Let me do some leg work on my end. I haven't played around with FIRRTL transforms so I need to look at some examples of how to apply it.
This appears it's on a per Module basis (I'm not 100% sure, so correct me if I'm wrong), I believe what @starbrilliance and myself were wondering is there a way...
Ah thanks for the tip! I will check that out. Probably what I need.
Hi @hukangha I haven't tried anything out. I have a custom perl script which allows me to prefix modules so I've just been using that for now. I plan to...
Hi @Dolu1990 , Thanks for the feedback. Would it be possible/advisable to add something in the SpinalConfig (like a subCompOutputBind) that could default to true but be overridden during generation...
So if I replace with ```referencesOverrides(io) = nameOfTheCorrespondingPinYouWant``` I still seem to get an assign statement. Could you point me to the area of code where the assigns are created...